Brigham Young University

In a previous paper it was shown that reducing the amount of glitches in digital designs can significantly reduce the amount of dynamic power consumption. Pipelined multipliers and a bit-serial multiplier design were used to show this. The paper failed to mention how much of the dynamic power consumption was due to the clock distribution. Also the only digitserial multiplier digit size investigated was a digit size of 1. This paper addresses the issue of dynamic clocking power and includes results of digit-serial multipliers with larger digit sizes.